Integration at wafer level
The highest integration densities possible in heterogeneous assemblies are achieved using wafer-level integration. All
processing steps are carried out at wafer level after the actual front-end processes have been completed. The packages we develop have lateral widths almost identical to the chip dimensions. We also include active and passive components on the wafer in interlayers and even higher integration densities are achieved with 3D integration using through-silicon vias (TSV).